The disclosed embodiments of the present invention relate to storing data into a memory device, and more particularly, to a memory address mapping method for controlling storage of images (e.g., fields) in a memory device by using a bank interleaving technique and memory address mapping circuit thereof.
Dynamic random access memory (DRAM) is a type of random access memory that stores each bit of data in a capacitor which serves as a memory cell. FIG. 1 is a diagram illustrating a conventional configuration of a DRAM device. The DRAM device 100 includes a plurality of row decoders 102_1-102_N, a plurality of column decoders 104_1-104_N, a plurality of banks 106_1-106_N, and a plurality of sense amplifiers 108_1-108_N. Each of the banks 106_1-106_N is accessed via one dedicated row decoder, one dedicated column decoder, and one dedicated sense amplifier, and includes a plurality of rows (i.e., pages) 110. The DRAM address for a memory cell may include a row address ADD_R, a column address ADD_C, and a bank address ADD_BA. The bank address ADD_BA determines which bank is selected, and the row address ADD_R determines which row (page) in the selected bank is selected. After bits located in the selected row (page) are loaded into the sense amplifier corresponding to the selected bank, the column address ADD_C determines which bit in the loaded bits contains information of the desired memory cell to be accessed. For example, in a case where the memory cell with a row address R1 and a column address C1 in bank 106_1 is a target memory cell to be accessed, the bank address ADD_BA selects the bank 106_1, the row decoder 102_1 corresponding to the bank 106_1 decodes the row address ADD_R to select a target row with the row address R1, the sense amplifier 108_1 corresponding to the bank 106_1 reads the target row, and then the column decoder 104_1 decodes the column address ADD_C to select a target bit addressed by the column address C1.
As shown in FIG. 1, each of the banks has its own sense amplifier, thereby allowing each of the banks to work independently. However, the bank conflict (or page miss) often causes the most significant performance degradation of the DRAM access. The bank conflict means that successive DRAM accesses are to access different rows in the same bank. To put it another way, as the row decoder for each bank is capable of accessing only one row in the corresponding bank, successive DRAM accesses on different rows of the same bank inevitably cause the bank conflict. For example, regarding bits loaded into the sense amplifier due to a current DRAM read request, a pre-charge command should be firstly issued to inform the sense amplifier to write stored bits back to the corresponding row. Secondly, an activation of another row to be accessed by the next DRAM read request is performed after the pre-charging is finished. It should be noted that several idle cycles must be inserted into two consecutive commands, where the number of idle cycles depends on types of the consecutive commands. In general, there is a pre-charge-to-active latency TRP between the pre-charge command and the activation command. After the row is activated, a read command should be issued. Similarly, there is an active-to-read latency TRCD between the activation command and the read command. In the end, the requested data will be shown on a data bus after a read-to-data latency TCAS. Briefly summarized, when the bank conflict (page miss) occurs, the activation of the page accessed by the next DRAM access must wait until pre-charging of contents of the page loaded in the sense amplifier by the current DRAM access (i.e., writing contents in the sense amplifier back to the corresponding page accessed by the current DRAM access) is finished. As one can see, data is successfully accessed after several idle cycles due to the pre-charge-to-active latency TRP, the active-to-read latency TRCD, and the read-to-data latency TCAS. If the bank conflict occurs frequently, the DRAM performance will be dramatically degraded.
In certain image processing applications (e.g., temporal noise reduction, motion adaptive de-interlacing, motion judder cancellation, and super-resolution scaling), the information which lies within temporally neighboring images may be referenced. However, when more images are used as references, more DRAM bandwidth is required. Unfortunately, higher requirement of the DRAM bandwidth usually implies higher hardware cost. In order to lower the hardware cost without reducing the number of reference images, raising the DRAM efficiency becomes one possible solution. As mentioned above, the bank conflict (page miss) is a key factor of the DRAM efficiency degradation. How to effectively reduce the occurrence of bank conflicts during the DRAM accesses becomes an important issue to be solved by designers in this field.